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[VHDL-FPGA-Verilog] spi_master_phy

Description: 这是spi接口传输的一部分内容，本源码一共三部分，功能：spi接口的的实现即对外设的读写数据-This is the spi interface transfer part of the contents of a total of three parts of this source, function: spi interface that the realization of the read and write data to the peripheral
Platform: | Size: 2048 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] spi_master

Description: SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps
Platform: | Size: 1024 | Author: guoguo | Hits:

[MPI] spi_verilog

Description: 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
Platform: | Size: 45056 | Author: davi_insist | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:

[Other] spi_tx

Description: 关于串口通讯(SPI)的VHDL源程序,可以在通用串口通讯中-On the serial communication (SPI) of the VHDL source code, can be general-purpose serial communication
Platform: | Size: 1024 | Author: mxc | Hits:

[Software Engineering] conjoined

Description: SPI protocol: Serial Periphral Interface with both slave and master incorporated-SPI protocol: Serial Periphral Interface with both slave and master incorporated
Platform: | Size: 1024 | Author: smik | Hits:

[VHDL-FPGA-Verilog] spi

Description: vhdl spi pin configuration
Platform: | Size: 1024 | Author: mohamad | Hits:

[VHDL-FPGA-Verilog] spi.asm

Description: vhdl spi port configuration
Platform: | Size: 2048 | Author: mohamad | Hits:

[VHDL-FPGA-Verilog] spi.sim

Description: vhdl spi cpld simulation
Platform: | Size: 4096 | Author: mohamad | Hits:

[VHDL-FPGA-Verilog] SPI_MISO

Description: SPI-MOSI程序,奇主机输出，从机输入-SPI
Platform: | Size: 1024 | Author: txc | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] VHDLsample

Description: 英国诺森比亚大学的vhdl语言例程集锦，英文原版。 包含很多优秀的VHDL语言范例，可供学习。所有程序均可在符合IEEE标准的模拟器上模拟。-This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in terms of basic logic gates, to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be synthesised using current synthesis tools.
Platform: | Size: 172032 | Author: eensy | Hits:

[VHDL-FPGA-Verilog] SPIVerilogHDL

Description: SPI协议Verilog HDL程序包用Verilog语言实现fpga模拟实现spi协议功能-fpga-spi-verilog
Platform: | Size: 84992 | Author: zhn | Hits:

[VHDL-FPGA-Verilog] simple_spi

Description: complete spi core written in vhdl. its easy to use and can be configured to operate at various clock frequencies. tested on an ADC to verify the operation
Platform: | Size: 584704 | Author: Shahzad | Hits:

[Parallel Port] spi

Description: SPI的两个程序，一个收，一个发，完整的工程-SPI' s two programs, an income, a hair
Platform: | Size: 5120 | Author: jolly | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] code

Description: spi接口 实现spi的传送 包括主从模式，时钟的建立。和数据的传送三部分-spi code very good for spi
Platform: | Size: 2048 | Author: 鲍鲍 | Hits:

[VHDL-FPGA-Verilog] spi_write

Description: 对spi接口的flash操作，用VHDL语言实现，read，write，擦除的接口电路控制-Spi interface on the flash operation, with the VHDL language, read, write, erase controls the interface circuit
Platform: | Size: 1024 | Author: 王伯祥 | Hits:

[VHDL-FPGA-Verilog] SpiMaster

Description: This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate
Platform: | Size: 9216 | Author: RutaliMulye | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI接口函数，实现双向通讯，速度12Mbps-SPI interface functions, two-way communication, speed of 12Mbps
Platform: | Size: 2048 | Author: shixu | Hits:
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